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DATA SHEET
COMPOUND TRANSISTOR
AA1L3M
on-chip resistor NPN silicon epitaxial transistor For mid-speed switching
FEATURES
* On-chip bias resistor (R1 = 4.7 k, R2 = 4.7 k) * Complementary transistor with AN1L3M
PACKAGE DRAWING (UNIT: mm)
ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
Parameter Collector to base voltage Collector to emitter voltage Emitter to base voltage Collector current (DC) Collector current (Pulse) Total power dissipation Junction temperature Storage temperature Symbol VCBO VCEO VEBO IC(DC) IC(pulse) * PT Tj Tstg Ratings 60 50 10 100 200 250 150 -55 to +150 Unit V V V mA mA mW C C
* PW 10 ms, duty cycle 50 %
ELECTRICAL CHARACTERISTICS (Ta = 25C)
Parameter Collector cutoff current DC current gain DC current gain Collector saturation voltage Low level input voltage High level input voltage Input resistance Resistance ratio Turn-on time Storage time Turn-off time Symbol ICBO hFE1 ** hFE2 ** VCE(sat) ** VIL ** VIH ** R1 R1/R2 ton tstg toff VCC = 5 V, RL = 1 k VI = 5 V, PW = 2 s duty cycle2 % Conditions VCB = 50 V, IE = 0 VCE = 5.0 V, IC = 5.0 mA VCE = 5.0 V, IC = 50 mA IC = 5.0 mA, IB = 0.25 mA VCE = 5.0 V, IC = 100 A VCE = 0.2 V, IC = 5.0 mA 3.0 3.28 0.9 20 70 40 140 0.08 1.1 1.5 4.7 1.0 6.11 1.1 0.5 3.0 5.0 0.3 0.8 MIN. TYP. MAX. 100 80 Unit nA - - V V V k -
s s s
** Pulse test PW 350 s, duty cycle 2 %
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. D16162EJ1V0DS00 (1st edition) Date Published April 2002 N CP(K) Printed in Japan
(c)
2002 1998
AA1L3M
TYPICAL CHARACTERISTICS (Ta = 25C)
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Data Sheet D16162EJ1V0DS
AA1L3M
Data Sheet D16162EJ1V0DS
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AA1L3M
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